In recent years, there have been great advancements in the speed, power, and complexity of integrated circuits, such as application specific integrated circuit (ASIC) chips, random access memory (RAM) chips, microprocessor (uP) chips, and the like. These advancements have made possible the development of system-on-a-chip (SOC) devices. An SOC device integrates into a single chip many of the components of a complex electronic system, such as a wireless receiver (i.e., cell phone, a television receiver, and the like). SOC devices greatly reduce the size, cost, and power consumption of the system.
SOC data processors are characterized by a very high degree of integration on a single integrated circuit (IC) chip. Many of the peripheral components now integrated onto the same IC chip as a processor core would have been implemented as separate IC chips in a previous generation of processors. Advantageously, this decreases the amount of board space required, reduces the effects of noise, allows for low-voltage operations, and, in many cases, reduces the pin count of the SOC device.
Typical SOC designs use an on-chip phase-locked loop (PLL) to generate clock signals that drive the SOC components. A typical reference clock signal produced by a PLL may be in the range of, for example, 200 MHz up to 2 GHz. However, while this type of design may be sufficient for ordinary operating conditions, the use of a PLL presents unique problems when designing and/or debugging an SOC chip. It often is desirable when testing or debugging a circuit to apply a selected number of clock cycles to the circuit-under-test and to then verify the state of certain test points or registers in the circuit-under-test. Also, it is desirable in many test procedures to apply the selected number of clock cycles at full speed, while manipulating the frequency or duty cycle of perhaps one or two individual clock cycles. This is very useful for identifying and debugging the critical speed paths of an integrated circuit design.
Unfortunately, doing this is difficult, if not impossible, with a PLL. Full speed testing with a PLL does not provide the ability to control the frequency and duty cycle of an individual clock cycle. To get around this, some test procedures may use an external test clock device to apply a selected number of clock cycles. However, for high-speed CPU designs, it is not possible to apply an input clock at speeds in excess of 300 MHz without also using special signaling. Moreover, even with an external clock, it is difficult to control the frequency and duty cycle of individual clock cycles in a high-speed clock signal (e.g., 400 MHz).
Therefore, there is a need in the art for improved system-on-a-chip (SOC) devices and other large-scale integrated circuits. In particular, there is a need for improved apparatuses and methods for applying a selected number of high-speed clock cycles to an SOC device or other large-scale integrated circuit, while manipulating the duty cycle and/or phase of an individual clock cycle.